Institute of Information Theory and Automation

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Department of Signal Processing

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SP Logo Our group focuses on the research, development and implementation of advanced digital signal and image processing algorithms, mainly in the fields of telecom, audio processing and scene analysis (image segmentation, motion detection). We build on our experience with the Bayesian approach to recursive identification of linear systems with time variable parameters.

Our target platforms are Field-Programmable Gate Arrays (FPGAs). We are focused mostly on embedded SoC solutions based on Xilinx Kintex, Zynq and ZynqULTRASCALE+ devices programmed by Xilinx Vivado and SDSoC tools. We also use Matlab/Simulink or OpenCV library to specify, model and verify algorithms which we subsequently convert and synthesize to FPGAs using HLS tools. That is why we also study features which result in fast execution, small memory footprint, small chip area and low power consumption. This is achieved through designing new DSP algorithms or modifying the existing DSP algorithms and by exploiting advanced architectural properties of FPGA circuits. Our aim is not only to deal with the theoretical design of algorithms but also to help industrial partners to solve implementation issues in all their complexity.

Currently we focus our development mainly around Zynq and ZynqULTRASCALE+ FPGA family boards from Xilinx and from Trenz (industrial and automotive grade ones).

Our aim is not only to deal with the theoretical design of algorithms but also to help industrial partners to solve implementation issues in all their complexity. The key partner is Technical Development of SKODA AUTO a.s. where we have main competence in development electronic systems for testing Human-Machine-Interface.

The department also continues in developing methods of Bayesian statistics towards estimation of mixtures with different distribution of components. The theory is used in practical applications (The Municipality of the capital city Prague, Motol University Hospital) and also lectured in Faculty of Transportation Sciences CTU, Prague.

Our department participated in several RTD projects supported by Framework Programmes of the EU as well as national grant agencies. Nowadays our group takes part in RTD projects financed by ECSELJoint Undertaking.

Among further activities belongs e.g. long-term participation in development international technical standards in Working Groups ISO.

admin: 2018-06-14 09:46

Department detail

Ing. Jiří Kadlec CSc.
Mgr. Milada Kadlecová
Ing. Lukáš Kohout
Bc. Veronika Kyznarová
Ing. Raissa Likhonina
Ing. Radim Matulík
Doc. Ing. Ivan Nagy CSc.
Ing. David Pavlík
Dr. Ing. Jiří Plíhal
Ing. Zdeněk Pohl Ph.D.
Doc. Ing. Evženie Suzdaleva CSc.
Václav Vaněk
Duration: 2015 - 2017
The proposed project deals with the issues of clustering and classification from the viewpoint of Bayesian methodology and using the recursive mixture estimation theory.
Duration: 2014 - 2017
The aim of this project is to define parameters representing skid resistance and longitudinal road unevenness on the base of evaluation vehicle data, available on CAN bus and that are shared between different vehicle assistant systems like ABS or ASR, e.g.
Duration: 2014 - 2017
EMC2 project addresses the ARTEMIS Innovation Pilot Programme AIPP5: Computing platforms for embedded systems. The objective of the EMC2 project is to foster changes through an innovative and sustainable service-oriented architecture approach for mixed criticality applications in dynamic and changeable real-time environments. EMC2 project focuses on the industrialization of European research
Duration: 2014 - 2017
ALMARVI project targets low-power adaptive platform solution for healthcare, smart phone and security industries which are as part of big societal challenges affordable healthcare and wellbeing and green and safe transportation. ALMARVI aims at providing cross-domain many-core platform solution, system software stack, tool chain, and adaptive algorithms that will enable massive data-rate image/
Duration: 2014 - 2017
PANACHE is the ENIAC KET Pilot Line project addresses subprogram 6. Design technologies and 7. Semiconductor process and integration. PANACHE project objective is to set-up a pilot line for embedded Flash technology design and manufacturing platform for the prototyping of innovative microcontrollers in Europe.
Duration: 2014 - 2017
THINGS2DO is the ENIAC KET Pilot Line project addresses subprogram 3. Energy Efficiency, 6. Design technologies and 4. Health and Ageing Socity. THINGS2DO project is focused on building the Design and Development Ecosystem for FD-SOI-technology. This technology is uniquely positioned to take advantage of some very distinct strengths of the European Semiconductor Industry.