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Conference Paper (international conference)
FPGA-based fault simulator
,
: Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits adn Systems, p. 274-278 , Eds: Reorda M. S., Novák O., Straube B.
: DDECS 2006. IEEE Design and Diagnostics of Electronic Circuits and Systems, (Prague, CZ, 18.04.2006-21.04.2006)
: CEZ:AV0Z10750506
: 1QS108040510, GA AV ČR
: falut simulation, FPGA, reconfiguartion
(eng): This paper describes a simulator based an this technique and show that partial dynamic reconfiguration is an effective way of falut injection. Error-detection-code based CED circuits are used in experiments; the results of the experiments are reported.
(cze): Článek presentuje simulátor chyb založený na programovatelném logickém poli.
: 09G, 09H
: JC