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Conference Paper (international conference)
Pipelined implementations of the A Priory Error-Feedback LSL algorithm using logarithmic arithmetic
, , ,
: Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing, p. 2681-2684
: IEEE, (Orlando 2002)
: ICASSP 2002, (Orlando, US, 13.05.2002-17.05.2002)
: CEZ:AV0Z1075907
: 33544, ESPRIT
: LNS, DSP, FPGA, floating-point, logarithmic arithmetic
(eng): In this paper we present several implementations of the Modified A Priori Error-Feedback LSL (EF-LSL) algorithm on the Virtex FPGA. Its computational parallelism and pipelinabilty are important advantages. Internally, the computations are based on the logarithmic number system. We compare 32-bit (SINGLE-ALU or DUAL-ALU version) and 20-bit (QUADRI-ALU versions). We show that the LNS implementation can outperform the standard DSP solution based on 32-bit floating-point processors.
: 09G, 09H
: JC