Institute of Information Theory and Automation

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Bibliography

Conference Paper (Czech conference)

Integrated iterative approach to FPGA placement

Daněk Martin

: Počítačové Architektury & Diagnostika PAD 2003, p. 43-50 , Eds: Kotásek Z., Růžička R., Sekanina L.

: VUT, (Brno 2003)

: PAD 2003 Počítačové Architektury & Diagnostika, (Zvíkovské Podhradí, CZ, 24.09.2003-26.09.2003)

: CEZ:AV0Z1075907

: 0210413, CTU

: FPGA placement, global routing, integrated approach

(eng): This paper describes a new iterative method based on an integrated timing-driven approach to the FPGA layout synthesis. The method uses a global routing to assess the quality of a placement. The placement and routing algorithms use an unified nonlinear cost function that takes into account both area and delay constraints imposed by a design, and eliminates effects of different signal net routing orders.

: 09G, 09H

: JC

2019-01-07 08:39