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Video Input/Output IP Cores for Xilinx ZCU102 with Avnet HDMI Input/Output FMC Module

Kohout Lukáš, Kadlec Jiří, Pohl Zdeněk

: ( 2019)

: 8A18013, GA MŠk

: system level compiler, HW acceleration, programmable logic array

: http://sp.utia.cz/index.php?ids=results&id=zcu102-hio

(eng): The functional sample describes video IP cores interfacing a video input and output of the Xilinx ZCU102 evaluation board with Avnet HDMI Input/Output FMC module. The system is designed with Xilinx Vivado 2018.3 tool.

: JC

: 20206

2019-01-07 08:39
Institute of Information Theory and Automation